1. Field of the Invention
The present invention relates to an input/output control circuit employing MOSFET transistors, and also relates to a microcomputer containing the input/output control circuit therein.
2. Description of the Related Art
FIG. 7 is a block diagram showing the conventional input/output control circuit for use in a microcomputer or the like. In the figure, reference numeral 31 denotes a voltage source having a voltage level VCC, numeral 32 denotes a ground portion having a voltage level VSS, 33 denotes an output P-channel transistor (hereinafter may be referred to just as a xe2x80x9cP-channel transistorxe2x80x9d), 34 denotes a an output N-channel transistor (hereinafter may be referred to just as an xe2x80x9cN-channel transistorxe2x80x9d), 35 denotes a pull-up P-channel transistor, 36 denotes an input/output terminal, 37 and 38 denote NAND gates, 39 denotes a NOR gate, 40 and 41 denote inverters, 42 denotes an input control gate, 43 denotes an output control gate, 44 denotes a pull-up control register, 45 denotes a direction register, 46 denotes a port latch, 47 denotes an output control register and numeral 48 denotes a data bus. Here, the pull-up control register 44, the direction register 45, the port latch 46 and the output control register 47 are all one-bit registers in which data can be written by way of the data bus 48.
The operation of the input/output control circuit of the above configuration is now explained below.
In the case where the input/output control circuit shown in FIG. 7 is used only as an input port (this mode of use may be referred to just as a xe2x80x9cnon pull-up port inputxe2x80x9d hereinafter), first xe2x80x9c0xe2x80x9d is written into the direction register 45. Since an output signal from the direction register 45 is of the xe2x80x9cLxe2x80x9d level, an xe2x80x9cHxe2x80x9d level signal is output from the NAND gate 38, whereas since an xe2x80x9cHxe2x80x9d level signal is input to the NOR gate 39 by way of the inverter 40, an xe2x80x9cLxe2x80x9d level signal is output from the NOR gate 39. Subsequently, the P-channel transistor 33 and the N-channel transistor 34 are set to OFF, and the input/output terminal 36 is thus set to a high impedance state. In this state, if an xe2x80x9cHxe2x80x9d level or an xe2x80x9cLxe2x80x9d level voltage is externally applied to the input/output terminal 36, the corresponding signal is transmitted to the data bus by way of the input control gate 42, and transmitted further to the inner circuit (not shown).
Next, in the case where not only the input/output control circuit shown in FIG. 7 is used as an input port, but is used also for pulling up the input signal (this mode of use may be referred to just as a xe2x80x9cpull-up port inputxe2x80x9d hereinafter), xe2x80x9c1xe2x80x9d is first written into the pull-up control register 44. In this case, since the P-channel transistor 35 is set to ON by way of the NAND gate 37, the input/output terminal is pulled up to the VCC level. Here, if the output mode of an external circuit (not shown) connected to the input/output terminal 36 is an N-channel open drain or the like, then the external circuit is set either in the xe2x80x9cLxe2x80x9d level or in the high-impedance state. When the external circuit is set in the high-impedance state, the potential of the input/output control terminal 36 is pulled up to the level of the VCC by the P-channel transistor 35. This xe2x80x9cHxe2x80x9d level signal is transmitted to the data bus by way of the input control gate 42, and is further transmitted to the internal circuit. On the other hand, when an xe2x80x9cLxe2x80x9d level signal is input from the external circuit, the operation of the input/output control circuit is same as that of the aforementioned case in which it is used as an input port without the pull-up operation.
Next, in the case where the input/output control circuit is used as an output port of a CMOS circuit (this mode of use may be referred to just as a xe2x80x9cCMOS-port outputxe2x80x9d hereinafter), first xe2x80x9c1xe2x80x9d is written into the direction register 45. In this case, the P-channel transistor 35 is set to OFF by way of the NAND gate 37. Thereafter, the data to be output is written into the port latch 46. In this state, if xe2x80x9c0xe2x80x9d is written into the port latch 46, the P-channel transistor 33 is set to OFF and the N-channel transistor 34 is set to ON by way of the NAND gate 38, the NOR gate 39 and the inverter 40, so that the input/output terminal 36 outputs a VSS-level voltage. On the other hand, if xe2x80x9c1xe2x80x9d is written into the port latch 46, the P-channel transistor 33 is set to ON and the N-channel transistor 34 is set to OFF by way of the same NAND gate 38, the NOR gate 39 and the inverter 40, so that the input/output terminal 36 outputs a VCC-level voltage.
Next, in the case where the input/output control circuit is used as an output port for a specified signal instead of being used as the CMOS-port output (this mode of use may be referred to just as a xe2x80x9cspecified-signal outputxe2x80x9d hereinafter), it is necessary to write xe2x80x9c0xe2x80x9d in the direction register, xe2x80x9c0xe2x80x9d in the pull-up control register, and xe2x80x9c1xe2x80x9d in the output control register.
In consideration of all this above, FIG. 8 shows the combinations of the logics set in the pull-up control register, in the direction register and in the output control register of the input/output control circuit shown in FIG. 7, together with the mode of use formed by each of the combinations. Since 3 bits in total can be set by these registers, the number of possible combinations is as many as 23, namely 8 combinations. Among these 8 combinations, efficiently used combinations are those corresponding to the above-mentioned 4 cases; namely the non pull-up port input, the pull-up port input, the CMOS-port output and the specified-signal output, so that the other 4 combinations are invalid.
Since the conventional input/output control circuit is configured as such, circuit configuration as a whole contains redundancy as invalid combinations are contained therein. Thus, there has been a problem that the redundancy contained therein makes the whole size of the circuit larger, resulting in a low cost performance. These defects are made more obvious when a plurality of ports each composed of an input/output control circuit of the same configuration are incorporated in one semiconductor chip, and the total redundancy is thus enlarged as a whole.
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide an input/output control circuit having same functions as those of the conventional circuit, but of a small size with high efficiency, by removing the redundant portions of the same circuit.
The input/output control circuit according to a first aspect of the present invention is constructed in such a manner that it comprises: a first transistor connected between the input/output terminal and a voltage source, a second transistor connected between the input/output terminal and a ground portion, a third transistor connected between the input/output terminal and the voltage source, in parallel with the first transistor, an input control gate connected to the input/output terminal for controlling transmission of input signals, an output control gate connected to the input/output terminal for controlling transmission of specific signals, a direction register for determining the direction indicating as to which of input and output operation is to be performed, a control register for determining the mode of input or output, and a selection circuit, which is connected to the gates respectively of the first transistor, the second transistor, and of the third transistor, the control terminals respectively of the input control gate and the output control gate, the direction register, and also connected to the control register.
The input/output control circuit according to another aspect of the present invention is constructed such that when a value indicating a signal input direction is input to the direction register and a value indicating a non pull-up input is input to the control register, the selection circuit outputs signals for setting the first, second, and third transistors to OFF, setting the input control gate to ON, and for setting the output control gate to OFF.
The input/output control circuit according to another aspect of the present invention is constructed such that when a value indicating a signal input direction is input to the direction register and a value indicating a pull-up input is input to the control register, the selection circuit outputs signals for setting the first and second transistors to OFF, the third transistor to ON, the input control gate to ON, and for setting the output control gate to OFF.
The input/output control circuit according to another aspect of the present invention is constructed such that when a value indicating a signal output direction is input to the direction register and a value indicating a CMOS-port output is input to the control register, the selection circuit outputs signals for setting the third transistor, the input control gate and the output control gate to OFF, which signal further setting the first transistor to ON and the second transistor to OFF in the case where an output data is xe2x80x9c1xe2x80x9d, and setting the first transistor to OFF and the second transistor to ON in the case where an output data is xe2x80x9c0xe2x80x9d.
The input/output control circuit according to further aspect of the present invention is constructed such that when a value indicating a signal output direction is input to the direction register and a value indicating output of a specific signal is input to the control register, the selection circuit outputs signals for setting the first, second and third transistors and also the input control gate to OFF, and for setting the output control gate to ON.
The input/output control circuit according to still further aspect of the present invention is constructed such that when a value indicating a signal input direction is input to the direction register and a value indicating a non pull-up input is input to the control register, the selection circuit outputs signals for setting the first, second, and third transistors to OFF, setting the input control gate to ON, and for setting the output control gate to OFF, when a value indicating a signal input direction is input to the direction register and a value indicating a pull-up input is input to the control register, the selection circuit outputs signals for setting the first and second transistors to OFF, the third transistor to ON, the input control gate to ON, and for setting the output control gate to OFF, when a value indicating a signal output direction is input to the direction register and a value indicating a CMOS-port output is input to the control register, the selection circuit outputs signals for setting the third transistor, the input control gate and the output control gate to OFF, which signals further setting the first transistor to ON and the second transistor to OFF in the case where an output data is xe2x80x9c1xe2x80x9d, and setting the first transistor to OFF and the second transistor to ON in the case where an output data is xe2x80x9c0xe2x80x9d, and when a value indicating a signal output direction is input to the direction register and a value indicating a specific-signal output is input to the control register, the selection circuit outputs signals for setting the first, second and third transistors and also the input control gate to OFF, and for setting the output control gate to ON.
A microcomputer according to the present invention is composed of one chip equipped with a plurality of input/output control circuits, wherein each of the input/output control circuits is composed of the same components as those of the input/output control circuit according to the first aspect of the present invention, thereby to enable 4 modes; namely the non pull-up port input, the pull-up port input, the CMOS-port output, and the specified-signal output.